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19-2740; Rev 0; 1/03
KIT ATION EVALU ILABLE AVA
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining
General Description
The MAX1960/MAX1961/MAX1962 high-current, highefficiency voltage-mode step-down DC-DC controllers operate from a 2.35V to 5.5V input and generate output voltages down to 0.8V at up to 20A. An on-chip charge pump generates a regulated 5V for MOSFET drive. Additionally, adaptive dead-time drivers allow a wide variety of MOSFETs to be used without risking shoot-through. Fixed-frequency PWM operation and external synchronization make these controllers suitable for telecom and datacom applications. The operating frequency is programmable to either 500kHz or 1MHz, or from 450kHz to 1.2MHz with an external clock. A clock output is provided to synchronize another converter for 180 out-of-phase operation. A high closed-loop bandwidth provides excellent transient response for applications with dynamic loads. Lossless current sensing in the MAX1960 and MAX1961 is achieved by monitoring the drain-to-source voltage of the low-side external FET. The current limit is scalable to accommodate a wide variety of MOSFETs and load currents. The MAX1962 has 10% accurate sense-resistor-based current limiting. The MAX1960 and MAX1962 have an adjustable output voltage from 0.8V to 4.95V. The MAX1961 and MAX1962 have four preset output voltages (1.5V, 1.8V, 2.5V, and 3.3V) and feature 0.5% voltage accuracy over temperature, line, and load variations. The MAX1960 and MAX1961 also feature voltage-margining control inputs that shift the output voltage up or down by 4% for system testing.
Features
o 0.5% Accurate Output o Operates from 2.35V to 5.5V Supply o Generates Low Output Voltage Down to 0.8V o o o o o o o o On-Chip Charge Pump Provides 5V Gate Drive Ceramic or Electrolytic Capacitors 94% Efficiency External Synchronization from 450kHz to 1.2MHz 500kHz/1MHz Fixed-Frequency PWM Operation Fast Transient Response Two Converters Can Operate 180 Out-of-Phase 4% Voltage Margining for System Test
MAX1960/MAX1961/MAX1962
o 10% Accurate Current Sensing (MAX1962) o Adaptive Dead Time Prevents Shoot-Through
Ordering Information
PART MAX1960EEP MAX1961EEP MAX1962EEP TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 20 QSOP 20 QSOP 20 QSOP
Typical Operating Circuit
INPUT 2.35V TO 5.5V
C+ VCC
CAVDD
MAX1960
VDD
Applications
ASIC, FPGA, DSP, and CPU Core and I/O Voltages Cellular Base Stations Telecom and Network Equipment Server and Storage Systems
VOLTAGE MARGINING AND ON/OFF
CTL1 BST CTL2 COMP DH OUTPUT 0.8 TO 0.87 VIN UP TO 20A
REF
LX
DL GND PGND
ILIM OPTIONAL SYNCHRONIZATION FSET/SYNC
Pin Configurations and Selector Guide appear at the end of the data sheet.
CLKOUT 180 OUT-OF-PHASE
CLKOUT
FB
________________________________________________________________ Maxim Integrated Products
1
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
ABSOLUTE MAXIMUM RATINGS
VCC, CTL_, CS, FSET/SYNC, SEL, EN, OUT to GND ..........................................................-0.3V to +6V ILIM, COMP, REF, FB, CLKOUT, C- to GND ..............................................-0.3V to VAVDD + 0.3V C+ to GND.............-0.3V to higher of VVCC + 1V or VVDD + 0.3V VDD, AVDD to GND ..............-0.3V to higher of VVCC - 0.3V or 6V DL to PGND ................................................-0.3V to VVDD + 0.3V BST to GND ............................................................-0.3V to +12V DH to LX ...................................................................-0.3V to +6V LX to BST..................................................................-6V to +0.3V PGND to GND, or VDD to AVDD ............................-0.3V to +0.3V Continuous Power Dissipation (TA = +70C) 20-Pin QSOP (derate up to +70C)..............................727mW 20-Pin QSOP (derate above +70C) ........................9.1mW/C Operating Temperature Range (Extended).........-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VVCC = 3.3V, Circuits of Figures 9-12, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER VCC Input Voltage Range VCC Input Voltage UVLO VDD Input Voltage UVLO Output Voltage MAX1960/MAX1962 (measured at FB) DC Output Accuracy SEL = GND MAX1961/ SEL = REF MAX1962 (FB = VDD), SEL not connected measured at output SEL = VDD MAX1960/MAX1961 MAX1960/MAX1961 0V to full load VVCC = 2.7V to 5.5V -0.2 1 In shutdown FSET/SYNC = GND FSET/SYNC = VCC f = 1MHz f = 500kHz 450 880 450 80 90 83 92 11 15 15 2 10 1280 500 1000 550 1120 1200 Rising or falling, hysteresis = 33mV (typ) Rising or falling, hysteresis = 44mV (typ) CONDITIONS MIN 2.35 1.95 3.9 0.8 0.796 1.492 1.791 2.487 3.272 +3.8 -3.8 0.800 1.500 1.800 2.500 3.300 +4 -4 0.08 0.1 +0.2 3 100 0.804 1.508 1.809 2.514 3.336 +4.2 -4.2 % % % % A mS cycles kHz kHz % % mA A V TYP MAX 5.5 2.3 4.45 UNITS V V V V
Positive Voltage-Margining Shift Negative Voltage-Margining Shift Load Regulation Error Line Regulation Error FB Input Bias Current Feedback Transconductance COMP Discharge Resistance DC-DC Soft-Start Time Switching Frequency SYNC Frequency Range Maximum Duty Cycle Maximum Duty Cycle Quiescent Supply Current Shutdown Supply Current
2
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining
ELECTRICAL CHARACTERISTICS (continued)
(VVCC = 3.3V, Circuits of Figures 9-12, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER CONDITIONS 2.7V VVCC 5.5V, ILOAD = 1mA to 50mA VDD Output Voltage 2.35V VVCC 2.7V, ILOAD = 1mA to 35mA, C1 = 4.7F, C6 = 22F (Note 1) 2.35V VVCC 3.6V with tripler, ILOAD = 1 to 50mA (circuit of Figure 12) (Note 1) Reference Voltage (No Load) Reference Load Regulation Positive Current-Limit Threshold (VPGND - VLX) Negative Current-Limit Threshold (VLX - VPGND) CS Bias Current OUT Bias Current Current-Limit Threshold (Positive Direction, Fixed, VPGND - VLX) Current-Limit Threshold (Negative Direction, Fixed, VLX - VPGND) Current-Limit Threshold (Positive Direction, Adjustable, VPGND - VLX) Current-Limit Threshold (Negative Direction, Adjustable, VLX - VPGND) Thermal-Shutdown Threshold DH Gate-Driver On-Resistance DL Gate-Driver On-Resistance (Pullup) DL Gate-Driver On-Resistance (Pulldown) Minimum Adaptive Dead Time FSET/SYNC Pulse Width FSET/SYNC Rise/Fall Time CTL_, FSET/SYNC, EN Input High Voltage CTL_, FSET/SYNC, EN Input Low Voltage CTL_, FSET/SYNC, EN Input Current CLKOUT VOL CLKOUT VOH CLKOUT Rise/Fall Time Sinking 1mA Sourcing 1mA CLOAD = 100pF (Note 1) VVCC 0.2V -50A to +50A VOUT = 0.8V MAX1962 VOUT = 2.0V VOUT = 3.3V MAX1962, VOUT = 0.8V to 3.3V MAX1962, VCS = 3.3V MAX1961/MAX1962, VOUT = 3.3V MAX1960/MAX1961, ILIM = VDD MAX1960/MAX1961, ILIM = VDD MAX1960/MAX1961, RILIM = 160k RILIM = 400k MAX1960/MAX1961, RILIM = 160k RILIM = 400k 15C hysteresis VBST - VLX = 5V, pulling up or down DL high state DL low state DH falling to DL rising DH rising to DL falling Minimum high time (Note 1) Minimum low time (Note 1) (Note 1) VVCC = 2.35V to 5.5V VVCC = 2.35V to 5.5V -1 0.01 VVCC 0.01V 40 2.0 0.8 +1 0.1 200 200 100 58 50 100 250 90 245 44 45 38 38 MIN 4.75 4.45 4.75 1.269 1.280 3 53 50 48 50 20 30 74 67 114 279 107 271 +160 1.8 1.8 0.5 35 26 TYP MAX 5.25 5.25 5.25 1.291 62 55 58 68 50 50 90 85 135 306 125 296 3.5 3.5 1.6 mV A A mV mV mV mV C ns ns ns V V A V V ns mV UNITS V V V V mV
MAX1960/MAX1961/MAX1962
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
ELECTRICAL CHARACTERISTICS
(VVCC = 3.3V, Circuits of Figures 9-12, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER VCC Input Voltage Range VCC Input Voltage UVLO VDD Input Voltage UVLO Output Voltage MAX1960/MAX1962 (measured at FB) SEL = GND DC Output Accuracy MAX1961/MAX1962 (FB = VDD), measured at output MAX1960/MAX1961 MAX1960/MAX1961 SEL = REF SEL not connected SEL = VDD Positive Voltage-Margining Shift Negative Voltage-Margining Shift FB Input Bias Current Feedback Transconductance COMP Discharge Resistance Switching Frequency SYNC Frequency Range Maximum Duty Cycle Maximum Duty Cycle Quiescent Supply Current Shutdown Supply Current 2.7V VVCC 5.5V, ILOAD = 1mA to 50mA VDD Output Voltage 2.35V VVCC 2.7V, ILOAD = 1mA to 35mA, C1 = 4.7F, C6 = 22F 2.35V VVCC 3.6V with tripler, ILOAD = 1mA to 50mA (circuit of Figure 12) Reference Voltage (No Load) Positive Current-Limit Threshold (VCS - VOUT) Negative Current-Limit Threshold (VOUT - VCS) CS Bias Current OUT Bias Current Current-Limit Threshold (Positive Direction, Fixed, VPGND - VLX) Current-Limit Threshold (Negative Direction, Fixed, VLX - VPGND) Current-Limit Threshold (Positive Direction, Adjustable, VPGND - VLX) MAX1962, VOUT = 2V MAX1962, VOUT = 2V MAX1962, VCS = 3.3V MAX1961/MAX1962, VOUT = 3.3V MAX1960/MAX1961, ILIM = VDD MAX1960/MAX1961, ILIM = VDD MAX1960/MAX1961, RILIM = 160k RILIM = 400k 58 50 100 250 4.75 4.45 4.75 1.267 45 42 f = 1MHz f = 500kHz In shutdown FSET/SYNC = GND FSET/SYNC = VCC 450 880 450 80 90 15 15 5.25 5.25 5.25 1.291 56 64 50 50 90 85 135 306 V mV mV A A mV mV mV V Rising or falling Rising or falling CONDITIONS MIN 2.35 1.95 3.90 0.8 0.795 1.492 1.789 2.482 3.272 3.8 -3.8 -0.2 1 0.805 1.508 1.809 2.517 3.339 4.2 -4.2 +0.2 3 100 550 1120 1200 % % A S kHz kHz % % mA A V TYP MAX 5.50 2.3 4.45 UNITS V V V V
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining
ELECTRICAL CHARACTERISTICS (continued)
(VVCC = 3.3V, Circuits of Figures 9-12, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER Current-Limit Threshold (Negative Direction, Adjustable, VLX - VPGND) DH Gate-Driver On-Resistance DL Gate-Driver On-Resistance (Pullup) DL Gate-Driver On-Resistance (Pulldown) FSET/SYNC Pulse Width FSET/SYNC Rise/Fall Time CTL_, FSET/SYNC, EN Input High Voltage CTL_, FSET/SYNC, EN Input Low Voltage CTL_, FSET/SYNC, EN Input Current CLKOUT VOL CLKOUT VOH CLKOUT Rise/Fall Time Sinking 1mA Sourcing 1mA CLOAD = 100pF VVCC 0.2V 40 VVCC = 2.35V to 5.5V VVCC = 2.35V to 5.5V -1 2.0 0.8 +1 0.1 RILIM = 400k VBST - VLX = 5V, pulling up or down DL high state DL low state Minimum high time Minimum low time 200 200 100 CONDITIONS MAX1960/MAX1961, RILIM = 160k MIN 90 245 TYP MAX 125 296 3.5 3.5 1.6 UNITS mV ns ns V V A V V ns
MAX1960/MAX1961/MAX1962
Note 1: Guaranteed by design. Note 2: Specifications at -40C are guaranteed by design, and not production tested.
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
Typical Operating Characteristics
(Circuit of Figure 9, TA = +25C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT WITH 15A 1MHz CIRCUIT, 3.3V INPUT
MAX1960 toc01
EFFICIENCY vs. LOAD CURRENT WITH 15A 1MHz CIRCUIT, 5V INPUT
MAX1960 toc02
EFFICIENCY vs. LOAD CURRENT WITH 15A 500kHz CIRCUIT, 3.3V INPUT
VOUT = 2.5V
MAX1960 toc03
100 VOUT = 2.5V 90 EFFICIENCY (%)
100
VOUT = 3.3V
100
90 EFFICIENCY (%)
90 EFFICIENCY (%)
80 VOUT = 1.8V 70 VOUT = 1.5V 60
80 VOUT = 2.5V 70 VOUT = 1.8V VOUT = 1.5V 60
80 VOUT = 1.8V 70 VOUT = 1.5V
60
50 0.1 1 10 100 LOAD CURRENT (A)
50 0.1 1 10 100 LOAD CURRENT (A)
50 0.1 1 10 100 LOAD CURRENT (A)
EFFICIENCY vs. LOAD CURRENT WITH 15A 500kHz CIRCUIT, 5V INPUT
MAX1960 toc04
OUTPUT VOLTAGE vs. INPUT VOLTAGE, 1MHz
MAX1960 toc05
OUTPUT VOLTAGE vs. INPUT VOLTAGE, 500kHz
3.3V OUTPUT
MAX1960 toc06
100
VOUT = 3.3V
3.5 3.0 OUTPUT VOLTAGE (V) 2.5 DROPOUT 2.0 1.5 1.0 0.5 15A LOAD 1.8V OUTPUT 1.5V OUTPUT 1.2V OUTPUT 3.3V OUTPUT
3.5 3.0 OUTPUT VOLTAGE (V) 2.5 2.0 1.5 1.0 0.5 15A LOAD 0 DROPOUT 1.8V OUTPUT 1.5V OUTPUT 1.2V OUTPUT
90 EFFICIENCY (%) VOUT = 2.5V VOUT = 1.8V 70 VOUT = 1.5V
2.5V OUTPUT
2.5V OUTPUT
80
60
50 0.1 1 10 100 LOAD CURRENT (A)
0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 INPUT VOLTAGE (V)
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
INPUT VOLTAGE (V)
FB REGULATION VOLTAGE vs. LOAD CURRENT
MAX1960 toc07
FREQUENCY vs. INPUT VOLTAGE
1100 FSET/SYNC = VCC 1000 FREQUENCY (kHz) 900 800 700 600
MAX1960 toc08
0.803 0.802 FB VOLTAGE (V) 0.801 0.800 0.799 0.798
1200
FSET/SYNC = GND 500 400 3.0 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V)
0.797 0 5 10 LOAD CURRENT (A) 15 20
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining
Typical Operating Characteristics (continued)
(Circuit of Figure 9, TA = +25C, unless otherwise noted.)
CHARGE-PUMP OUTPUT VOLTAGE vs. CHARGE-PUMP LOAD CURRENT, 1MHz
MAX1960 toc10 MAX1960 toc09
MAX1960/MAX1961/MAX1962
FREQUENCY vs. TEMPERATURE
1100 1000 900 FREQUENCY (kHz) 800 700 600 500 400 300 200 100 0 -40 -15 10 35 60 85 TEMPERATURE (C) 4.5 FSET/SYNC = GND FSET/SYNC = VCC 5.2 CHARGE-PUMP OUTPUT VOLTAGE (V) 5.1 5.0 4.9
CHARGE-PUMP OUTPUT VOLTAGE vs. CHARGE-PUMP LOAD CURRENT, 500kHz
CHARGE-PUMP OUTPUT VOLTAGE (V) C1 = 1F C6 = 4.7F
MAX1960 toc11
C1 = 0.47F C6 = 2.2F
5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 VIN = 2.5V
VIN = 3.3V 4.8 4.7 4.6 VIN = 2.5V
VIN = 3.3V
0
50
100
150
200
0
50
100
150
200
CHARGE-PUMP LOAD CURRENT (mA)
CHARGE-PUMP LOAD CURRENT (mA)
TRIPLER CHARGE-PUMP OUTPUT VOLTAGE vs. CHARGE-PUMP LOAD CURRENT, 1MHz
MAX1960 toc12
TRIPLER CHARGE-PUMP OUTPUT VOLTAGE vs. CHARGE-PUMP LOAD CURRENT, 500kHz
CHARGE-PUMP OUTPUT VOLTAGE (V) C10, C11, C12 = 1F C6 = 4.7F
MAX1960 toc13 MAX1960 toc15
5.2 CHARGE-PUMP OUTPUT VOLTAGE (V) 5.1 5.0 4.9 4.8 4.7 4.6 CIRCUIT OF FIGURE 12 4.5 0 10 20 30 40 VIN = 2.5V C10, C11, C12 = 0.47F C6 = 2.2F
5.2 5.1 5.0 4.9 4.8 4.7 4.6 CIRCUIT OF FIGURE 12 4.5
VIN = 2.5V
50
0
10
20
30
40
50
CHARGE-PUMP LOAD CURRENT (mA)
CHARGE-PUMP LOAD CURRENT (mA)
MAX1960/MAX1961 CURRENT-LIMIT THRESHOLD VOLTAGE vs. TEMPERATURE
CURRENT-LIMIT THRESHOLD VOLTAGE (mV)
MAX1960 toc14
MAX1962 CURRENT-LIMIT THRESHOLD VOLTAGE vs. TEMPERATURE
52.0 CURRENT-LIMIT THRESHOLD VOLTAGE (mV) 51.5 51.0 50.5 50.0 49.5 49.0 48.5 48.0 47.5 47.0 -40 -15 10 35 60 85
350 300 250 200 150 100 50 0 -40 -15 10 35 60 ILIM = VDD RILIM = 390k
85
TEMPERATURE (C)
TEMPERATURE (C)
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
Typical Operating Characteristics (continued)
(Circuit of Figure 9, TA = +25C, unless otherwise noted.)
7.5A TO 15A TO 7.5A LOAD TRANSIENT
MAX1960 toc16
VOLTAGE-MARGINING STEP RESPONSE
MAX1960 toc17
CTL1 CTL2 VOUT 50mV/div
5V/div 5V/div
IIN
200mA/div
ILOAD
5A/div
VOUT CIRCUIT OF FIGURE 13
200mV/div
20s/div
50s/div
STARTUP/SHUTDOWN WAVEFORMS
MAX1960 toc18
MAX1960/MAX1961 SHORT-CIRCUIT WAVEFORMS
MAX1960 toc19
VOUT IIN 10A/div
CIRCUIT OF FIGURE 13 2V/div
IL
10A/div IL 20A/div
VOUT
1V/div IIN 1ms/div 50s/div 5A/div
MAX1962 SHORT-CIRCUIT WAVEFORMS
MAX1960 toc20
SYNC TIMING WAVEFORMS
MAX1960 toc21
DH MASTER IIN 10A/div DL MASTER CLKOUT MASTER/ SYNC SLAVE DH SLAVE DL SLAVE 200ns/div
IL
10A/div
VOUT VIN = 5V VOUT = 3.3V 50s/div
2V/div
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining
Pin Description
PIN NAME MAX1960 MAX1961 MAX1962 Clock Output. Connect to FSET/SYNC of a second converter to operate 180 out-ofphase. CLKOUT swings from VCC to GND. CLKOUT is low in shutdown (see the Operating Frequency and Synchronization section). Frequency Set and Synchronization. Connect to GND for 500kHz operation, connect to VCC for 1MHz operation, or drive with clock signal to synchronize (between 450kHz and 1200kHz). Current Limit. Connect a resistor from ILIM to GND to set the current-sense threshold voltage. Connect ILIM to VDD to select the default threshold of 75mV. Enable. Drive high for normal operation. Drive low or connect to GND for shutdown mode. Preset Output Voltage Select. Allows the output to be set to one of four preset voltages (1.5V, 1.8V, 2.5V, and 3.3V). For the MAX1962, FB must be connected to VDD if SEL is to be used (see the Setting the Output Voltage section). No Connection. Not internally connected. Output. Connect to the output. Used to sense the output voltage for internal feedback and current sense. Control Pins. Controls voltage margining and shutdown. Connect both CTL1 and CTL2 high for normal operation. Connect both CTL1 and CTL2 low for shutdown. Connect CTL1 high and CTL2 low for +4% voltage margining. Connect CTL1 low and CTL2 high for -4% voltage margining. If voltage margining is not to be used, connect CTL1 and CTL2 together and use to enable/shutdown the device. Current-Sense Input. Connect to the junction of the current-sense resistor and the inductor. The MAX1962 current-sense threshold is 50mV measured from CS to OUT. Filtered Supply from VDD. Connect a 1F bypass capacitor. AVDD is forced to VCC in shutdown. Do not apply an external load to AVDD. Feedback Input. The feedback threshold is 0.8V. Connect to the center of a resistive voltage-divider from the output to GND to set the output voltage to 0.8V or greater. On the MAX1962, connect FB to VDD to select preset output voltages (see SEL). Compensation Pin. COMP is forced to GND in shutdown, UVLO, or thermal fault. Reference Output. VREF = 1.28V. Bypass with a 0.22F capacitor to GND. Analog Ground. Connect to the PC board analog ground plane. Connect the PC board analog ground plane and power ground planes with a single connection. Charge-Pump Output. Provides regulated 5V to power the IC and gate drivers. Bypass with a 4.7F ceramic capacitor for operating frequencies between 450kHz and 950kHz. Bypass with a 2.2F ceramic capacitor for 1MHz operation. VDD is internally forced to VCC in shutdown. Do not apply an external load to VDD. Low-Side MOSFET Synchronous Rectifier Gate-Driver Output. DL is high in shutdown. Power Ground. Connect to the PC board power ground plane. FUNCTION
MAX1960/MAX1961/MAX1962
1
1
1
CLKOUT
2
2
2
FSET/SYNC
3 -- -- 4 --
3 -- 4 -- 8
-- 3 4 -- 5
ILIM EN SEL N.C. OUT
5
5
--
CTL1
6
6
--
CTL2
-- 7
-- 7
6 7
CS AVDD
8 9 10 11
-- 9 10 11
8 9 10 11
FB COMP REF GND
12
12
12
VDD
13 14
13 14
13 14
DL PGND
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
Pin Description (continued)
PIN NAME MAX1960 MAX1961 MAX1962 15 16 17 18 19 20 15 16 17 18 19 20 15 16 17 18 19 20 CC+ VCC BST DH LX Charge-Pump Flying Capacitor Negative Connection. Use a 0.47F ceramic capacitor at 1MHz, and 1F between 450kHz and 950kHz. Charge-Pump Flying Capacitor Positive Connection. Use a 0.47F ceramic capacitor at 1MHz and 1F between 450kHz and 950kHz. Input Supply to Charge Pump Boost Capacitor Connection. Connect a 0.1F ceramic capacitor from BST to LX. High-Side MOSFET Gate-Driver Output. DH is low in shutdown. Inductor Connection FUNCTION
Detailed Description
The MAX1960/MAX1961/MAX1962 are high-current, high-efficiency voltage-mode step-down DC-DC controllers that operate from 2.35V to 5.5V input and generate adjustable voltages down to 0.8V at up to 20A. An on-chip charge pump generates a regulated 5V for driving a variety of external N-channel MOSFETs. Constant frequency PWM operation and external synchronization make these controllers suitable for telecom and datacom applications. The operating frequency is programmed externally to either 500kHz or 1MHz, or from 450kHz to 1.2MHz with an external clock. A clock output is provided to synchronize another converter for 180 out-of-phase operation. A high closed-loop bandwidth provides excellent transient response for applications with dynamic loads.
where IAVDD is the current supplied to the IC through AV DD (typically 2mA), f OSC is the PWM switching frequency, Q G1 is the gate charge of the high-side MOSFET, and QG2 is the gate charge of the low-side MOSFET. The MOSFETs must be chosen such that ITOTAL does not exceed 50mA. For example, with 1MHz operation, QG1 + QG2 should be less than 48nC.
Voltage Margining and Shutdown
The voltage-margining feature on the MAX1960/ MAX1961 shifts the output voltage up or down by 4%. This is useful for the automatic testing of systems at high and low supply conditions to find potential hardware failures. CTL1 and CTL2 control voltage margining as outlined in Table 1. A shutdown feature is included on all three parts, which stops switching the output drivers and the charge pump, reducing the supply current to less than 15A. For the MAX1962, drive EN high for normal operation, or low for shutdown. For the MAX1960/MAX1961, drive both CTL1 and CTL2 high for normal operation, or drive CTL1 and CTL2 low for shutdown. For a simple enable/shutdown function with no voltage margining, connect CTL1 and CTL2 together and drive as one input.
Internal Charge Pump
An on-chip regulated charge pump develops 5V at 50mA (max) with input voltages as low as 2.35V. The output of this charge pump provides power for the internal circuitry, bias for the low-side driver (DL), and the bias for the boost diode, which supplies the highside MOSFET gate driver (DH). The charge pump is synchronized with the DL driver signal and operates at 1/2 the PWM frequency. The external MOSFET gate charge is the dominant load for the charge pump and is proportional to the PWM switching frequency. The charge pump must supply chip-operating current plus adequate gate current for both MOSFETs at the selected operating frequency. The required charge-pump output current is given by the formula: ITOTAL = IAVDD + fOSC (QG1 + QG2)
10
Table 1. Voltage Margining Truth Table
CTL1 High High Low Low CTL2 High Low High Low FUNCTION Normal operation +4% output-voltage shift -4% output-voltage shift Shutdown
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
ILIM (MAX1960/MAX1961) OUT CLKOUT OSC FSET/SYNC UVLO LX OSC COMP COMP PGND OUT (MAX1961/MAX1962) ERROR AMP FB (MAX1960/MAX1962) FEEDBACK SELECT R Q VDD DL S Q DH CS (MAX1962) LX PGND BST
CURRENT SENSE
SOFT-START DAC
REF
AVDD REF VDD C+
VSEL (MAX1961/MAX1962)
MAX1960/ MAX1961/ MAX1962
SHUTDOWN AND VOLTAGE MARGINING
OSC
CHARGE PUMP CVCC
CTL1 (MAX1960/MAX1961) CTL2 (MAX1960/MAX1961) EN (MAX1962)
GND
Figure 1. Functional Diagram
MOSFET Gate Drivers
The DH and DL drivers are designed to drive logic-level N-channel MOSFETs to optimize system cost and efficiency. MOSFETs with RDSON rated at VGS 4.5V are recommended. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on until DL is fully off. There must be a low-resistance, low-inductance path from the DL driver to the MOSFET gate for the adaptive dead-time circuit to work properly. Otherwise, the internal sense circuitry could interpret the MOSFET gate as "off" while there is actually still charge left on the gate. Use very short, wide traces measuring no more than 20 squares (50mils to 100mils wide if the MOSFET is 1in from the IC).
Undervoltage Lockout and Soft-Start
There are two undervoltage lockout (UVLO) circuits on the MAX1960/MAX1961/MAX1962. The first UVLO circuit monitors VCC, which must be above 2.15V (typ) in order for the charge pump to operate. The second UVLO circuit monitors the output of the charge pump. The charge-pump output, VDD, must be above 4.2V (typ) in order for the PWM converter to operate. Both UVLO circuits inhibit switching and force DL high and DH low when either VCC or VDD are below their threshold. When the monitored voltages are above their thresholds, an internal soft-start timer ramps up the erroramplifier reference voltage. The ramp occurs in eighty 10mV steps. Full output voltage is reached 1.28ms after activation with a 1MHz operating frequency.
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
Operating Frequency and Synchronization
The MAX1960/MAX1961/MAX1962 operating frequency is set externally to either 500kHz or 1MHz. For 500kHz operation, connect FSET/SYNC to GND, or for 1MHz operation, connect FSET/SYNC to VDD. Alternately, an external clock from 450kHz to 1.2MHz can be applied to SYNC. A clock output (CLKOUT) that is 180 out-of-phase with the internal clock is also provided. This allows a second converter to be synchronized, and operate 180 out-ofphase with the first. To do this, simply connect CLKOUT of the first converter to FSET/SYNC of the second converter. The first converter can be set internally to 500kHz or 1MHz for this mode of operation. When the first converter is synchronized to an external clock, CLKOUT is the inverse of external clock. See the SYNC Timing Waveform in the Typical Operating Characteristics. increases until it reaches its maximum value, where the part enters dropout. With a switching frequency of 1MHz, the maximum duty cycle is about 83%. At 500kHz, the duty cycle can increase to about 92%, resulting in a lower dropout voltage. The duty cycle is dependent on the input voltage (VIN), the output voltage (V OUT ), and the parasitic voltage drops in the MOSFETs and the inductor (V DROP(N1), V DROP(N2), V DROP(L)). Note that V DROP(L) includes the voltage drop due to the inductor's resistance, the drop across the current-sense resistor (if used), and any other resistive voltage drop from the LX switching node to the point where the output voltage is sensed. The duty cycle is found from: D= VOUT + VDROP(L) VIN - VDROP(N1) - VDROP(N2)
Lossless Current Limit (MAX1960/MAX1961)
To prevent damage in the case of excessive load current or a short circuit, the MAX1960/MAX1961 use the low-side MOSFET's on-resistance (RDS(ON)) for current sensing. The current is monitored during the on-time of the low-side MOSFET. If the current-sense voltage (VPGND - VLX) rises above the current-limit threshold for more than 128 clock cycles, the controller turns off. The controller remains off until the input voltage is removed or the device is re-enabled with CTL1 and CTL2 (see the Setting the Current Limit section).
Adaptive Dead Time
The MAX1960/MAX1961/MAX1962 DL and DH MOSFET drivers have an adaptive dead-time circuit to prevent shoot-through current caused by high- and low-side MOSFET overlap. This allows a wide variety of MOSFETs to be used without matching FET dynamic characteristics. The DL driver will not go high until DH drives the high-side MOSFET gate to within 1V of its source (LX). The DH output will not go high until DL drives the low-side MOSFET gate to within 1V of ground.
Design Procedure
Component selection is primarily dictated by the following criteria: Input voltage range. The maximum value (VIN(MAX)) must accommodate the worst-case high input voltage. The minimum value (VIN(MIN)) must account for the lowest input voltage after drops due to connectors, fuses, and selector switches are considered. Maximum load current. There are two values to consider: The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements and is key in determining output capacitor requirements. ILOAD(MAX) also determines the inductor saturation rating and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and is key in determining input capacitor requirements, MOSFET requirements, as well as those of other critical heatcontributing components.
Current-Sense Resistor (MAX1962)
The MAX1962 uses a standard current-sense resistor in series with the inductor for a 10% accurate current-limit measurement. The current-sense threshold is 50mV. This provides accurate current sensing at all duty cycles without relying on MOSFET on-resistance. CS connects to the high-side (inductor side) of the current-sense resistor and OUT connects to the low-side (output side) of the current-sense resistor. The current-sense resistor for the MAX1962 may also be replaced with a series RC network across the inductor. This method uses the parasitic resistance of the inductor for current sensing. This method is less accurate than using a current-sense resistor, but is lower cost and provides slightly higher efficiency. See the Design Procedure section for instructions on using this method.
Dropout Performance
The MAX1960/MAX1961/MAX1962 enter dropout when the input voltage is not sufficiently high to maintain output regulation. As input voltage is lowered, the duty cycle
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining
Inductor operating point. This choice provides tradeoffs between size, transient response, and efficiency. Choosing higher inductance values results in lower inductor ripple current, lower peak current, lower switching losses, and, therefore, higher efficiency at the cost of slower transient response and larger size. Choosing lower inductance values results in large ripple currents, smaller size, and poorer efficiency, but have faster transient response.
MAX1960/MAX1961/MAX1962
Table 2. Preset Voltages-- MAX1961/MAX1962
PRESET OUTPUT VOLTAGE 1.5V 1.8V 2.5V 3.3V SEL GND REF No connection VDD
Setting the Output Voltage
The MAX1961 has four output voltage presets selected by SEL. Table 2 shows how each of the preset voltages are selected. The MAX1962 also has four preset output voltages, but also is adjustable down to 0.8V. To use the preset voltages on the MAX1962, FB must be connected to VDD. SEL then selects the output voltage as shown in Table 2. Both the MAX1960/MAX1962 feature an adjustable output that can be set down to 0.8V. To set voltages greater than 0.8V, Connect FB to a resistor-divider from the output (Figures 9 and 11). Use a resistor up to 10k for R2 and select R1 according to the following equation: V R1 = R2 x OUT - 1 VFB where the feedback threshold, VFB = 0.8V, and VOUT is the output voltage.
C10, C11, C12 C6 D2 D3 C11 C10 VCC CC+ VDD R5 10 AVDD C4 1F C6 C12 D4 D5
MAX1960/ MAX1961/ MAX1962
500kHz 1F 4.7F
1MHz 0.47F 2.2F
Input Voltage Range
The MAX1960/MAX1961/MAX1962 have an input voltage range of 2.35V to 5.5V but cannot operate at both extremes with one application circuit. The standard charge-pump doubler application circuit operates with an input range of 2.7V to 5.5V (Figures 9, 10, and 11). In order to operate down to 2.35V, the charge pump must be configured as a tripler. This circuit, however, limits the maximum input voltage to 3.6V. The schematic for the tripler charge pump is shown in Figure 2. Note that the flying capacitor between C+ and C- has been removed and C+ is not connected.
Figure 2. Tripler Charge-Pump Configuration.
vides a good compromise between efficiency and economy. Choose a low-loss inductor having the lowest possible DC resistance. Ferrite core type inductors are often the best choice for performance. The inductor saturation current rating must exceed IPEAK: LIR IPEAK = ILOAD(MAX) + x ILOAD(MAX) 2
Inductor Selection
Determine an appropriate inductor value with the following equation: L = VOUT x VIN - VOUT VIN x fOSC x LIR x ILOAD(MAX)
Setting the Current Limit
Lossless Current Limit (MAX1960/MAX1961) The MAX1960/MAX1961 use the low-side MOSFET's onresistance (RDS(ON)) for current sensing. This method of current limit sets the maximum value of the inductor's "valley" current (Figure 3). If the inductor current is higher than the valley current-limit setting at the end of the clock period, the controller skips the DH pulse. When the first current-limit event is detected, the controller initi13
The inductor current ripple, LIR, is the ratio of peak-topeak inductor ripple current to the average continuous inductor current. An LIR between 20% and 40% pro-
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
DH IPEAK LX ILOAD INDUCTOR CURRENT R R = 33 C C = 4.7F 0.22H, 2.8mW, ILIMIT = 18A RL L
MAX1962
IVALLEY
DL
CS OUT
TIME
Figure 3. Inductor Current Waveform
Figure 4. Using the Inductor Resistance as a Current-Sense Resistor with the MAX1962
ates a 128 clock cycle counter. If the current limit is present at the end of this count, the controller remains off until the input voltage is removed and re-applied, or the device is re-enabled with CTL1 and CTL2. The 128-cycle counter is reset when four successive DH pulses are observed, without activating the current limit. At maximum load, the low excursion of inductor current, IVALLEY(MAX), is: LIR IVALLEY(MAX) = ILOAD(MAX) - x ILOAD(MAX) 2 The current-limit threshold (VCLT) is set by connecting a resistor (RILIM) from ILIM to GND. The range for this resistor is 100k to 400k. Set current-limit threshold as follows: VCLT = RILIM x 0.714A Connecting ILIM to VDD sets the threshold to a default value of 75mV. To prevent the current limit from falsely triggering, VCLT divided by the low-side MOSFET RDS(ON) must exceed the maximum value of IVALLEY. The maximum value of low-side MOSFET RDS(ON) should be used: VCLT > RDS(ON)MAX x IVALLEY(MAX) A limitation of sensing current across MOSFET on-resistance is that the MOSFET on-resistance varies significantly from MOSFET to MOSFET and over temperature. Consequently, this current-sensing method may not be suitable if a precise current limit is required. If better
accuracy is needed, use the MAX1962 with a currentsense resistor. Current-Sense Resistor (MAX1962) The MAX1962 uses a current-sense resistor connected from the inductor to the output with Kelvin sense connections. The current-sense voltage is measured from CS to OUT, and has a fixed threshold of 50mV. The MAX1962 current limit is triggered when the peak voltage across the current-sense resistor, IPEAK x RSENSE, exceeds 50mV. Once current sense is triggered, the controller does not turn off, but continues to operate at the current limit. This method of current sensing is more precise due to the accuracy of the current-sense resistor. The cost of this precision is that it requires an extra component and is slightly less efficient due to the loss in the currentsense resistance. Inductor Resistance Current Sense (MAX1962) Alternately, the inductor resistance can be used to sense current in place of a current-sense resistor. To do this, connect a series RC network in parallel with the inductor (Figure 4). Choose a resistor value less than 40 to avoid offsets due to CS input current. Calculate the capacitor value from the formula C = 2L / (RL x R). The effective current-sense resistance (RSENSE) equals RL. Current-sense accuracy then depends on the accuracy of the inductor resistance. Note that the currentsense signal is delayed due to the RC filter time constant. Consequently, inductor current may overshoot (by as much as 2x) when a fast short occurs.
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining
Output Capacitor Selection
The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and load transient requirements. In addition, the capacitance value must be high enough to absorb the inductor energy during load steps. In applications where the output is subject to large load transients, low ESR is needed to prevent the output from dipping too low (VDIP) during a load step: RESR VDIP ILOADSTEP(MAX) The RMS input ripple current is given by: IRMS = ILOAD x VOUT x (VIN - VOUT ) VIN
MAX1960/MAX1961/MAX1962
For optimal circuit reliability, choose a capacitor that has less than 10C temperature rise at the peak ripple current.
Compensation and Stability
Compensation with Ceramic Output Capacitors The high switching frequency range of the MAX1960/MAX1961/MAX1962 allows the use of ceramic output capacitors. Since the ESR of ceramic capacitors is very low typically, the frequency of the associated transfer function zero is higher than the unity-gain crossover frequency and the zero cannot be used to compensate for the double pole created by the output inductor and capacitor. The solution is Type 3 compensation (Figure 5), which takes advantage of local feedback to create two zeros and three poles (Figure 6). The frequency of the poles and zeros are described below: fP1 = 0 fP2 = fP3 = 1 2 x R2 x C3 1 2 x R1 x 1 2 L 0 x C 0 C1 x C2 C1 + C2
In applications with less severe load steps, maximum ESR may be governed by what is needed to maintain acceptable output voltage ripple: RESR VRIPPLE(P-P)
LIR x ILOAD(MAX)
To satisfy both load step and ripple requirements, select the lowest value from the above two equations. The capacitor is usually selected by physical size, ESR, and voltage rating, rather than by capacitance value. With current tantalum, electrolytic, and polymer capacitor technology, the bulk capacitance will also be sufficient once the ESR requirement is satisfied. When using low-capacity filter capacitors such as ceramic, capacitor size is usually determined by the capacitance needed to prevent voltage undershoot and overshoot during load transients. The overshoot voltage (VSOAR) is given by: VSOAR = 2 x VOUT x COUT L x (IPEAK )2
fLC =
Generally, once enough capacitance is in place to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem.
fZ1 =
1 2 x R1 x C1
Input Capacitor Selection
The input capacitor (CIN) reduces the current peaks drawn from the input supply and reduces noise injection. The source impedance to the input supply largely determines the value of CIN. High source impedance requires high input capacitance. The input capacitor must meet the ripple current requirement (I RMS ) imposed by the switching currents.
fZ2 =
1 2 x (R2 + R3) x C3 1 2 x RESR x C0
fZESR =
Unity-gain crossover frequency: f0 = R1 x C3 x VIN(MAX) VRAMP x 1 2 x L 0 x C 0
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
VIN GAIN (dB) DH LO LX DL C0 VOUT
MAX1960
FB
R3 R2 R4 C3
R1 COMP fp1 C2 C1 fz1 fz2 fp2 fp3 FREQUENCY
Figure 5. Type 3 Compensation Network
Figure 6. Transfer Function for Type 3 Compensation
where: VIN(MAX) = Maximum input voltage VRAMP = Oscillator ramp voltage = 0.85 x 106/fS, where fS = switching frequency LO = Output inductance CO = Output capacitance The goal is to place the two zeros below crossover and the two poles above crossover so that crossover occurs with a single-pole slope. The compensation procedure is as follows: Select the crossover frequency such that: f0 < fZESR and f0 <1/5 fS Select R1 such that: R1 >> where gmEA = 2mS. Place the first zero before the double pole: 1 C1 2 x 0.75 x fLC x R1 Place the third pole at half the switching frequency: C2 1 2 x 0.5 x fS x R1 2 gmEA
If C2 < 10pF, it can be omitted. C3 2 x f0 x L 0 x C0 x VRAMP R1 x VIN
Place the second pole after the ESR zero: R2 If: R2 < 1 (= 550), gM 1 2 x fZESR x C3
increase R1 and recalculate C1, C2, and C3. Place the second zero at the double-pole frequency: R3 1 - R2 2 x fLC x C3
Set the output voltage: R4 = VFB x R3, VFB = 0.8V VOUT - VFB
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining
Compensation with Electrolytic Output Capacitors The MAX1960/MAX1961/MAX1962 use a voltage-mode control scheme that regulates the output voltage by comparing the error-amplifier output (COMP) with a fixed internal ramp to produce the required duty cycle. The inductor and output capacitor create a double pole at the resonant frequency, which has gain drop of 40dB per decade, and phase shift of 180. The error amplifier must compensate for this gain drop and phase shift in order to achieve a stable high-bandwidth, closed-loop system. The basic regulator loop consists of a power modulator, an output feedback divider and an error amplifier. The power modulator has DC gain set by VIN/VRAMP, with a double pole set by the inductor and output capacitor, and a single zero set by the output capacitor (CO) and its equivalent series resistance (ESR). Below are equations that define the power modulator: The DC gain of the power modulator is: GMOD(DC) = VIN VRAMP The transconductance error amplifier has DC gain GEA(dc) of 80dB. A dominant pole is set by the compensation capacitor (CC), the amplifier output resistance (RO), and the compensation resistor (RC): fPEA = 1 2 x CC x (R0 + RC )
MAX1960/MAX1961/MAX1962
A zero is set by the compensation resistor and the compensation capacitor: fZEA = 1 2 x CC x RC
The total closed-loop gain must equal to unity at the crossover frequency, where the crossover frequency should be higher than fZESR, so that the -1 slope is used to cross over at unity gain. Also, the crossover frequency should be less than or equal to 1/5 the switching frequency. f fZESR < fC S 5 The loop-gain equation at the crossover frequency is: VFB x GEA(fC ) x GMOD(fC ) = 1 VOUT where: GEA(fC ) = gmEA x RC and: GMOD(fC ) = GMOD(DC) x (fPMOD )2 fESR x fC
where VRAMP = 0.85 x 106 / fS. The pole frequency due to the inductor and output capacitor is: fPMOD = 1 2 LOCO
The zero frequency due to the output capacitor's ESR is: fZESR = 1 2 x RESR x CO
The output capacitor is usually comprised of several same value capacitors connected in parallel. With n capacitors in parallel, the output capacitance is: CO = n x CEACH The total ESR is: RESR = RESR(EACH) n
The compensation resistor, RC, is calculated from: RC = VOUT gmEA x VFB x GMOD(fC )
where gmEA = 2mS. Due to the under-damped (Q > 1) nature of the output LC double pole, the error-amplifier compensation zero should be approximately 0.2fPMOD to provide good phase boost. CC is calculated from: CC = 5 2 x RC x fPMOD
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The ESR zero (f ZESR ) for a parallel combination of capacitors is the same as for an individual capacitor. The feedback divider has a gain of GFB = VFB/VOUT, where VFB is 0.8V.
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
A small capacitor CF, can also be added from COMP to GND to provide high-frequency decoupling. CF will add another high-frequency pole (fPHF) to the error-amplifier response. This pole should be greater than 100 times the error-amplifier zero frequency to have negligible impact on the phase margin. This pole should also be less than half the switching frequency for effective decoupling: 100fZEA < fPHF < 0.5fS Select a value for fPHF in the range given above, then solve for CF using the following equation: CF = 1 2 x RC x fPHF The power modulator gain at fC is: GMOD(fc) = = VIN VRAMP x (fPMOD )2 fZESR x fC
3 (9201)2 x = 0.102 0.85 29.3k x 100k
Choose R1 = 8.06k, then R2 = 10k (see the Setting the Output Voltage section):
C=
VOUT 1.8 = gmEA x VFB x GMOD(fC ) 0.002 x 0.8 x 0.102
= 11k
Below is a numerical example to calculate compensation values: VIN = 3.3V VRAMP = 0.85V VOUT = 1.8V VFB = 0.8V IOUT(max) = 15A CO = 2 x 680F = 1360F ESR = 0.008 / 2 = 0.004 LO = 0.22H gmEA = 2mS fS = 1MHz fPMOD = = 1 2 x L O x CO 1
CC =
5 5 = = 7863pF 2 x RC x fPMOD 2 x 11k x 9201
Select C C = 8200pF (nearest standard capacitor value). Select fPHF in the range 100fZEA < fPHF < 0.5fS. 184kHz < fPHF < 500kHz Select fPHF = 250kHz, then solve for CF: CF = 1 2 x RC x fPHF = 1 = 58pF 2 x 11k x 250kHz
Select the nearest standard capacitor value CF = 56pF. Summary of feedback divider and compensation components: R1 = 8.06k R2 = 10k RC = 11k CC = 8200pF CF = 56pF
2 x 0.22 x 10-6 x 1360 x 10-6 = 9.201kHz fZESR = = 1 2 x CO x RESR 1
Power MOSFET Selection
When selecting a MOSFET, essential parameters include: (1) Total gate charge (QG) (2) Reverse transfer capacitance (CRSS) (3) On-resistance (RDS(ON)) (4) Gate threshold voltage (VTH(MIN)) (5) Turn-on/turn-off times (6) Turn-on/turn-off delays
2 x 1360 x 10-6 x 0.004 = 29.3kHz Choose the crossover frequency (fC) in the range fZESR < fC < fS/5: 29.3kHz < fC < 200kHz Select fC = 100kHz, this meets the criteria above, and the bandwidth is high enough for good transient response.
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
FEEDBACK DIVIDER V1 0.8V R1 Gm VIN/VRAMP RS R2 R3 L1 C9 V2 RESR COUT RLOAD ERROR AMPLIFIER MODULATOR OUTPUT FILTER
Figure 7. Open-Loop Transfer Model
At high switching rates, dynamic characteristics (parameters 1, 2, 5, and 6) that predict switching losses may have more impact on efficiency than RDS(ON), which predicts DC losses. QG includes all capacitance associated with charging the gate, and best performance is achieved with a low total gate charge. QG also helps predict the current needed to drive the gate at the selected operating frequency. This is very important because the output current from the charge pump is finite (50mA, max) and is used to drive the gates of the MOSFETs as well as provide bias for the IC. RDS(ON) is important as well, as it is used for current sensing in the MAX1960/MAX1961. RDS(ON) also causes power dissipation during the on-time of the MOSFET. Choose QG to be as low as possible. Ensure that: QG1 + QG2 50mA fS
Choose RDS(ON) to provide the desired ILOAD(MAX) at the desired current-limit threshold voltage (see the Setting the Current Limit section).
MOSFET RC Snubber Circuit Fast-switching transitions can cause ringing due to resonating circuit parasitic inductance and capacitance at the switching nodes. This high-frequency ringing occurs at LX rising and falling transitions, and may introduce current-sensing errors and generate EMI. To dampen this ringing, a series RC snubber circuit can be added across each MOSFET switch (Figure 8). Typical values for the snubber components are CSNUB = 4700pF and RSNUB = 1, however, the ideal values for snubber components will depend on circuit parasitics. Below is the procedure for selecting the component values of the series RC snubber circuit: 1) Connect a scope probe to measure VLX to GND, and observe the ringing frequency, fR. 2) Find the capacitor value (connected from LX to GND) that reduces the ringing frequency by half. 3) The circuit parasitic capacitance, CPAR, at LX is then equal to 1/3 of the value of the added capacitance above.
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
INPUT
RSNUB DH N1 CSNUB LX RSNUB N2 CSNUB PGND L1
MAX1960
DL
Figure 8. RC Snubber Circuit
where VIN(MAX) is the maximum value of the input voltage, tFALL and tRISE are the fall and rise time of the MOSFET, I L(PEAK) and I L(VALLEY) are the maximum peak and valley inductor current, and fS is the PWM switching frequency: IL(PEAK) = IOUT(MAX) x (1 + 0.5 x LIR) and IL(VALLEY) = IOUT(MAX) x (1 - 0.5 x LIR) where LIR is the peak-to-peak inductor ripple current divided by the load current. The total power dissipation in the high-side MOSFET is the sum of these two power losses: PD(N1) = PD(N1RESISTIVE) + PD(N1SWITCHING) For the low-side MOSFET, the worst-case power dissipation occurs at maximum input voltage:
VOUT PD(N2RESISTIVE) = 1 x ILOAD2 x RDS(ON) VIN(MAX)
4) The circuit parasitic inductance, LPAR, is calculated by: LPAR = 1 (2 x fR )2 x CPAR
Applications Information
PC Board Layout Guidelines
A properly designed PC board layout is important in any switching DC-DC converter circuit. If possible, mount the MOSFETs, inductor, input/output capacitors, and current-sense resistor on the top side. Connect the ground for these devices close together on a powerground trace. Make all other ground connections to a separate analog ground plane. Connect the analog ground plane to power ground at a single point. To help dissipate heat, place high-power components (MOSFETs, inductor, and current-sense resistor) on a large PC board area. Keep high-current traces short and wide to reduce the resistance in these traces. Also make the gate drive connections (DH and DL) short and wide, measuring 10 to 20 squares (50mils to 100mils wide if the MOSFET is 1in from the controller IC). For the MAX1960/MAX1961, connect LX and PGND to the low-side MOSFET using Kelvin sense connections. For the MAX1962, connect CS and OUT to the currentsense resistor using Kelvin sense connections. Place the REF capacitor, the BST diode and capacitor, and the charge-pump components as close as possible to the IC. If the IC is far from the input capacitors, bypass VCC to GND with a 0.1F or greater ceramic capacitor close to the VCC pin. For an example PC board layout, see the MAX1960 evaluation kit.
5) The resistor for critical dampening, RSNUB = 2 x fR x LPAR. The resistor value can be adjusted up or down to tailor the desired damping and the peak voltage excursion. 6) The capacitor, CSNUB, should be at least 2 to 4 times the value of the CPAR to be effective. 7) The snubber circuit power loss is dissipated in the resistor, PRSNUB, and can be calculated as: PRSNUB = CSNUB x (VIN )2 x fS where V IN is the input voltage, and f S is the switching frequency. Choose RSNUB power rating that exceeds the calculated power dissipation. MOSFET Power Dissipation Worst-case power dissipation occurs at duty factor extremes. For the high-side MOSFET, the worst-case power dissipation due to resistance occurs at minimum input voltage (VIN(MIN)): PD(N1RESISTIVE) = VOUT x ILOAD2 x RDS(ON) VIN(MIN)
The following formula calculates switching losses for the high-side MOSFET, but is only an approximation and not a substitute for evaluation:
PD(N1SWITCHING) =
(IL(PEAK) x
20
tFALL + IL(VALLEY) x tRISE x
)
VIN(MAX) 2
x fS
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
Table 3. Component List for Application Circuits
PART C1 C2 C3 C4 C5 C6 C8 C9 C10, C11, C12 C13, C14 D1 D2-D5 L1 N1 N2 R1 R2 R3 R4 R5 R6 R7, R8 APP. CIRCUIT 1, 2, 3 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 4 1, 2, 3, 4 1, 2, 3, 4 4 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 4 1, 3 1, 3 1, 2, 3, 4 1, 2 1, 2, 3, 4 3, 4 1, 2, 3, 4 15A OUTPUT 1MHz 0.47F ceramic capacitor 5 x 10F ceramic capacitors 2 x 680F POSCAPs Sanyo 2R5TPD680M8 1F ceramic capacitor 0.1F ceramic capacitor 2.2F ceramic capacitor 0.22F ceramic capacitor (Table 4) 0.47F ceramic capacitors 4700pF ceramic capacitors Schottky diode Central CMSSH-3 Schottky diodes Central CMHSH5-2L 0.22H, 1.7m inductor Sumida CDEP1040R2NC-50 N-channel MOSFET International Rectifier IRLR7821 N-channel MOSFET International Rectifier IRLR7833 Sets output voltage 10k 1% resistor (Table 4) 390k 5% resistor 10 5% resistor 1.5m 5%, 1W resistor Panasonic ERJM1WTJ1M5U 1 5% resistors 15A OUTPUT 500kHz 1F ceramic capacitor 5 x 10F ceramic capacitors 2 x 680F POSCAPs Sanyo 2R5TPD680M8 1F ceramic capacitor 0.1F ceramic capacitor 4.7F ceramic capacitor 0.22F ceramic capacitor (Table 5) 1F ceramic capacitors 4700pF ceramic capacitors Schottky diode Central CMSSH-3 Schottky diodes Central CMHSH5-2L 0.45H inductor Sumida CDEP1040R4MC-50 N-channel MOSFET International Rectifier IRLR7821 N-channel MOSFET International Rectifier IRLR7833 Sets output voltage 10k 1% resistor (Table 5) 390k 5% resistor 10 5% resistor 1.5m 5%, 1W resistor Panasonic ERJM1WTJ1M5U 1 5% resistors
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2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
Table 4. R1, R3, and C9 Component Values for 1MHz Operation
VIN 5V 3.3V 2.5V VOUT = 3.3V R1 (k) 3.12 -- -- R3 (k) 1.2 -- -- C9 (F) 0.0068 -- -- 2.13 -- -- VOUT = 2.5V R1 (k) R3 (k) 9.1 -- -- C9 (F) 0.01 -- -- R1 (k) 1.24 1.24 1.24 VOUT = 1.8V R3 (k) 6.8 2.7 3.9 C9 (F) 0.01 0.01 0.01 R1 () 876 876 876 VOUT = 1.5V R3 (k) 5.5 2.4 3.3 C9 (F) 0.01 0.01 0.01
Table 5. R1, R3, and C9 Component Values for 500kHz Operation
VIN 5V 3.3V 2.5V VOUT = 3.3V R1 (k) 3.12 -- -- R3 (k) 36 -- -- C9 (F) 0.0033 -- -- 2.13 2.13 -- VOUT = 2.5V R1 (k) R3 (k) 27 47 -- C9 (F) 0.0047 0.0033 -- R1 (k) 1.24 1.24 1.24 VOUT = 1.8V R3 (k) 20 30 39 C9 (F) 0.0068 0.0047 0.0033 R1 () 876 876 876 VOUT = 1.5V R3 (k) 16 27 33 C9 (F) 0.0068 0.0047 0.0033
Table 6. Component Suppliers
SUPPLIER Central Semiconductor International Rectifier Kamaya Murata Panasonic Sanyo Sumida Taiyo Yuden PHONE 631-435-1110 310-322-3331 260-489-1533 814-237-1431 714-373-7939 619-661-6835 847-956-0666 408-573-4150 WEBSITE www.centralsemi.com www.irf.com www.kamaya.com www.murata.com www.panasonic.com www.sanyo.com www.sumida.com www.t-yuden.com PART MAX1960 MAX1961 MAX1962 VOLTAGE MARGINING 4% No
Selector Guide
CURRENT LIMIT FET VDS Sensing 10% with RSENSE OUTPUT VOLTAGE Adjustable 4 Presets 4 Presets or Adjustable
22
______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
C1 INPUT 2.7V TO 5.5V VCC C2 R5 CTL1 VDD D1 CTL2 BST C6
C+
CAVDD
C4
COMP C9
MAX1960
R7 DH C5 N1 C13 L1 OUTPUT DOWN TO 0.8V C3 R8
REF
LX
R3
C8
DL
N2 C14
GND FSET/SYNC CLKOUT CLKOUT
PGND ILIM R4
R1
N.C.
FB R2
Figure 9. Application Circuit 1--MAX1960 Adjustable Output Voltage
______________________________________________________________________________________
23
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
C1 INPUT 2.7V TO 5.5V VCC C2 R5 CTL1 VDD D1 CTL2 BST C6
C+
CAVDD
C4
COMP C9
MAX1961
R7 DH C5 N1 C13 L1 OUTPUT 2.5V C3 R8
REF
LX
R3
C8
DL
N2 C14
GND FSET/SYNC CLKOUT CLKOUT
PGND ILIM R4
VSEL
OUT
Figure 10. Application Circuit 2--MAX1961 Preset Output Voltage
24
______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
C1 INPUT 2.7V TO 5.5V VCC C2 R5 VDD D1 EN BST C6
C+
CAVDD
C4
COMP C9
MAX1962
R7 DH C5 N1 C13 L1 R6 OUTPUT DOWN TO 0.8V C3 R8
REF
LX
R3
C8
DL
N2 C14
GND
PGND
FSET/SYNC CLKOUT
CS
CLKOUT
OUT R1
VSEL
FB R2
Figure 11. Application Circuit 3--MAX1962 Adjustable Output Voltage
______________________________________________________________________________________
25
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
D2 D3 D4 C11 D5
C10 INPUT 2.35V TO 3.6V VCC C2 R5 VDD D1 EN BST C6
C12
C+
CAVDD
C4
COMP C9
MAX1962
R7 DH C5 N1 C13 L1 R6 OUTPUT 1.5V C3 R8
REF
LX
R3
C8
DL
N2 C14
GND
PGND
FSET/SYNC CLKOUT
CS
CLKOUT
OUT
VSEL
FB
VDD
Figure 12. Application Circuit 4--MAX1962 Tripler Configuration, Preset Output
26
______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
C1 0.47F INPUT 2.7V TO 5.5V C2 5 x 10F VCC C+ CAVDD R5 10 CTL1 VDD D1 CTL2 BST C4 1F
C6 2.2F
COMP C10 33pF C9 820pF C8 0.22F
MAX1960
DH
C5 0.1F
N1
R7 1 C13 4700pF L1 R8 1 C14 4700pF OUTPUT 2.5V, 15A C3 4 x 47F TAIYO-YUDEN JMK325BJ476MN
REF
LX
R3 10k
DL
N2
GND FSET/SYNC CLKOUT CLKOUT
PGND ILIM R4 390k FB C7 560pF
R9 680
R1 6.84k
N.C.
R2 3.22k N1 - IRLR7821 N2 - IRLR7833
Figure 13. Application Circuit--Ceramic Output Capacitors with Type 3 Compensation
______________________________________________________________________________________
27
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining MAX1960/MAX1961/MAX1962
Pin Configurations
TOP VIEW
CLKOUT 1 FSET/SYNC 2 ILIM 3 N.C. (SEL) 4 CTL1 5 CTL2 6 AVDD 7 FB (OUT) 8 COMP 9 REF 10 20 LX 19 DH 18 BST 17 VCC
TOP VIEW
CLKOUT 1 FSET/SYNC 2 EN 3 SEL 4 OUT 5 CS 6 AVDD 7 FB 8 COMP 9 REF 10 20 LX 19 DH 18 BST 17 VCC
MAX1960 MAX1961
16 C+ 15 C14 PGND 13 DL 12 VDD 11 GND
MAX1962
16 C+ 15 C14 PGND 13 DL 12 VDD 11 GND
QSOP
( ) ARE FOR MAX1961.
QSOP
Chip Information
TRANSISTOR COUNT: 4476 PROCESS: BiCMOS
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______________________________________________________________________________________
2.35V to 5.5V, 0.5% Accurate, 1MHz PWM Step-Down Controllers with Voltage Margining
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
MAX1960/MAX1961/MAX1962
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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